| | |
| | | #include "scpi/error.h" |
| | | #include "scpi/fifo.h" |
| | | |
| | | // basic FIFO |
| | | /* basic FIFO */ |
| | | static fifo_t local_error_queue; |
| | | |
| | | |
| | | |
| | | void SCPI_ErrorInit(scpi_t * context) { |
| | | //// FreeRTOS |
| | | // context->error_queue = (scpi_error_queue_t)xQueueCreate(100, sizeof(int16_t)); |
| | | |
| | | // basic FIFO |
| | | /* |
| | | * // FreeRTOS |
| | | * context->error_queue = (scpi_error_queue_t)xQueueCreate(100, sizeof(int16_t)); |
| | | */ |
| | | |
| | | /* basic FIFO */ |
| | | context->error_queue = (scpi_error_queue_t)&local_error_queue; |
| | | fifo_init((fifo_t *)context->error_queue); |
| | | } |
| | |
| | | * @param context - scpi context |
| | | */ |
| | | void SCPI_ErrorClear(scpi_t * context) { |
| | | //// FreeRTOS |
| | | //xQueueReset((xQueueHandle)context->error_queue); |
| | | |
| | | // basic FIFO |
| | | /* |
| | | * // FreeRTOS |
| | | * xQueueReset((xQueueHandle)context->error_queue); |
| | | */ |
| | | |
| | | /* basic FIFO */ |
| | | fifo_clear((fifo_t *)context->error_queue); |
| | | } |
| | | |
| | |
| | | */ |
| | | int16_t SCPI_ErrorPop(scpi_t * context) { |
| | | int16_t result = 0; |
| | | |
| | | //// FreeRTOS |
| | | //if (pdFALSE == xQueueReceive((xQueueHandle)context->error_queue, &result, 0)) { |
| | | // result = 0; |
| | | //} |
| | | |
| | | // basic FIFO |
| | | |
| | | /* |
| | | * // FreeRTOS |
| | | * if (pdFALSE == xQueueReceive((xQueueHandle)context->error_queue, &result, 0)) { |
| | | * result = 0; |
| | | * } |
| | | */ |
| | | |
| | | /* basic FIFO */ |
| | | fifo_remove((fifo_t *)context->error_queue, &result); |
| | | |
| | | return result; |
| | |
| | | */ |
| | | int32_t SCPI_ErrorCount(scpi_t * context) { |
| | | int16_t result = 0; |
| | | |
| | | //// FreeRTOS |
| | | //result = uxQueueMessagesWaiting((xQueueHandle)context->error_queue); |
| | | |
| | | //basic FIFO |
| | | |
| | | /* |
| | | * // FreeRTOS |
| | | * result = uxQueueMessagesWaiting((xQueueHandle)context->error_queue); |
| | | */ |
| | | |
| | | /* basic FIFO */ |
| | | fifo_count((fifo_t *)context->error_queue, &result); |
| | | |
| | | |
| | | |
| | | return result; |
| | | } |
| | | |
| | | static void SCPI_ErrorPushInternal(scpi_t * context, int16_t err) { |
| | | //// FreeRTOS |
| | | //xQueueSend((xQueueHandle)context->error_queue, &err, 0); |
| | | |
| | | // basic FIFO |
| | | static void SCPI_ErrorAddInternal(scpi_t * context, int16_t err) { |
| | | /* |
| | | * // FreeRTOS |
| | | * xQueueSend((xQueueHandle)context->error_queue, &err, 0); |
| | | */ |
| | | |
| | | /* basic FIFO */ |
| | | fifo_add((fifo_t *)context->error_queue, err); |
| | | } |
| | | |
| | | struct error_reg { |
| | | int16_t from; |
| | | int16_t to; |
| | | scpi_reg_val_t bit; |
| | | }; |
| | | |
| | | #define ERROR_DEFS_N 8 |
| | | |
| | | static const struct error_reg errs[ERROR_DEFS_N] = { |
| | | {-100, -199, ESR_CER}, /* Command error (e.g. syntax error) ch 21.8.9 */ |
| | | {-200, -299, ESR_EER}, /* Execution Error (e.g. range error) ch 21.8.10 */ |
| | | {-300, -399, ESR_DER}, /* Device specific error -300, -399 ch 21.8.11 */ |
| | | {-400, -499, ESR_QER}, /* Query error -400, -499 ch 21.8.12 */ |
| | | {-500, -599, ESR_PON}, /* Power on event -500, -599 ch 21.8.13 */ |
| | | {-600, -699, ESR_URQ}, /* User Request Event -600, -699 ch 21.8.14 */ |
| | | {-700, -799, ESR_REQ}, /* Request Control Event -700, -799 ch 21.8.15 */ |
| | | {-800, -899, ESR_OPC}, /* Operation Complete Event -800, -899 ch 21.8.16 */ |
| | | }; |
| | | |
| | | /** |
| | | * Push error to queue |
| | | * @param context - scpi context |
| | | * @param err - error number |
| | | */ |
| | | void SCPI_ErrorPush(scpi_t * context, int16_t err) { |
| | | SCPI_ErrorPushInternal(context, err); |
| | | |
| | | // Command error (e.g. syntax error) ch 21.8.9 |
| | | if ((err < -100) && (err > -199)) { |
| | | SCPI_RegSetBits(context, SCPI_REG_ESR, ESR_CER); |
| | | } |
| | | |
| | | // Execution Error (e.g. range error) ch 21.8.10 |
| | | if ((err < -200) && (err > -299)) { |
| | | SCPI_RegSetBits(context, SCPI_REG_ESR, ESR_EER); |
| | | } |
| | | int i; |
| | | |
| | | // Device specific error -300, -399 ch 21.8.11 |
| | | if ((err < -300) && (err > -399)) { |
| | | SCPI_RegSetBits(context, SCPI_REG_ESR, ESR_DER); |
| | | } |
| | | SCPI_ErrorAddInternal(context, err); |
| | | |
| | | // Query error -400, -499 ch 21.8.12 |
| | | if ((err < -400) && (err > -499)) { |
| | | SCPI_RegSetBits(context, SCPI_REG_ESR, ESR_QER); |
| | | } |
| | | |
| | | // Power on event -500, -599 ch 21.8.13 |
| | | if ((err < -500) && (err > -599)) { |
| | | SCPI_RegSetBits(context, SCPI_REG_ESR, ESR_PON); |
| | | } |
| | | |
| | | // User Request Event -600, -699 ch 21.8.14 |
| | | if ((err < -600) && (err > -699)) { |
| | | SCPI_RegSetBits(context, SCPI_REG_ESR, ESR_URQ); |
| | | } |
| | | |
| | | // Request Control Event -700, -799 ch 21.8.15 |
| | | if ((err < -700) && (err > -799)) { |
| | | SCPI_RegSetBits(context, SCPI_REG_ESR, ESR_REQ); |
| | | } |
| | | |
| | | // Operation Complete Event -800, -899 ch 21.8.16 |
| | | if ((err < -800) && (err > -899)) { |
| | | SCPI_RegSetBits(context, SCPI_REG_ESR, ESR_OPC); |
| | | for(i = 0; i < ERROR_DEFS_N; i++) { |
| | | if ((err <= errs[i].from) && (err >= errs[i].to)) { |
| | | SCPI_RegSetBits(context, SCPI_REG_ESR, errs[i].bit); |
| | | } |
| | | } |
| | | |
| | | if (context) { |