Resolve #38 Error queue not empty bit
| | |
| | | } |
| | | |
| | | /** |
| | | * Emit no error |
| | | * @param context scpi context |
| | | */ |
| | | static void SCPI_ErrorEmitEmpty(scpi_t * context) { |
| | | if ((SCPI_ErrorCount(context) == 0) && (SCPI_RegGet(context, SCPI_REG_STB) & STB_QMA)) { |
| | | SCPI_RegClearBits(context, SCPI_REG_STB, STB_QMA); |
| | | |
| | | if (context->interface && context->interface->error) { |
| | | context->interface->error(context, 0); |
| | | } |
| | | } |
| | | } |
| | | |
| | | /** |
| | | * Emit error |
| | | * @param context scpi context |
| | | * @param err Error to emit |
| | | */ |
| | | static void SCPI_ErrorEmit(scpi_t * context, int16_t err) { |
| | | SCPI_RegSetBits(context, SCPI_REG_STB, STB_QMA); |
| | | |
| | | if (context->interface && context->interface->error) { |
| | | context->interface->error(context, err); |
| | | } |
| | | } |
| | | |
| | | /** |
| | | * Clear error queue |
| | | * @param context - scpi context |
| | | */ |
| | |
| | | |
| | | /* basic FIFO */ |
| | | fifo_clear((scpi_fifo_t *)context->error_queue); |
| | | |
| | | SCPI_ErrorEmitEmpty(context); |
| | | } |
| | | |
| | | /** |
| | |
| | | |
| | | /* basic FIFO */ |
| | | fifo_remove((scpi_fifo_t *)context->error_queue, &result); |
| | | |
| | | SCPI_ErrorEmitEmpty(context); |
| | | |
| | | return result; |
| | | } |
| | |
| | | } |
| | | } |
| | | |
| | | if (context) { |
| | | if (context->interface && context->interface->error) { |
| | | context->interface->error(context, err); |
| | | } |
| | | SCPI_ErrorEmit(context, err); |
| | | |
| | | if (context) { |
| | | context->cmd_error = TRUE; |
| | | } |
| | | } |
| | |
| | | err_buffer[0] = 0; |
| | | err_buffer_pos = 0; |
| | | |
| | | SCPI_RegClearBits(&scpi_context, SCPI_REG_STB, STB_QMA); |
| | | SCPI_EventClear(&scpi_context); |
| | | SCPI_ErrorClear(&scpi_context); |
| | | } |
| | |
| | | |
| | | srq_val = 0; |
| | | TEST_IEEE4882("ABCD\r\n", ""); /* "Undefined header" cause command error */ |
| | | CU_ASSERT_EQUAL(srq_val, 96); /* value of STB as service request */ |
| | | TEST_IEEE4882("*STB?\r\n", "96\r\n"); /* Event status register + Service request */ |
| | | CU_ASSERT_EQUAL(srq_val, (STB_ESR | STB_SRQ | STB_QMA)); /* value of STB as service request */ |
| | | TEST_IEEE4882("*STB?\r\n", "100\r\n"); /* Event status register + Service request */ |
| | | TEST_IEEE4882("*ESR?\r\n", "32\r\n"); /* Command error */ |
| | | |
| | | TEST_IEEE4882("*STB?\r\n", "0\r\n"); |
| | | TEST_IEEE4882("*STB?\r\n", "68\r\n"); /* Error queue is still not empty */ |
| | | TEST_IEEE4882("*ESR?\r\n", "0\r\n"); |
| | | |
| | | TEST_IEEE4882("SYST:ERR:NEXT?\r\n", "-113,\"Undefined header\"\r\n"); |
| | | TEST_IEEE4882("SYST:ERR:NEXT?\r\n", "0,\"No error\"\r\n"); |
| | | |
| | | TEST_IEEE4882("*STB?\r\n", "0\r\n"); /* Error queue is now empty */ |
| | | |
| | | RST_executed = FALSE; |
| | | TEST_IEEE4882("*RST\r\n", ""); |